Portable, battery powered devices, such as laptop computers and mobile telephones, require compact logic circuits that provide both high performance and low power consumption. It is also important that when the logic circuits in such devices are in an inactive, standby mode, their power consumption is as low as possible so that their drain on the battery is minimized.
As integrated circuit fabrication progresses to smaller geometry technologies, increased transistor performance is gained at the expense of increased leakage currents (also known as “high Ioff” currents). These leakage currents increase a circuit's power consumption, especially in standby modes, making the high performance, low power requirements of portable, battery powered devices more difficult to attain. Although specialized low-leakage, small geometry transistors can be designed by, for instance, increasing their gate oxide thickness and therefore threshold voltage, these transistors have a correspondingly lower performance, i.e., their switching rate is significantly slower.
In order to provide small geometry circuits with high performance and low power consumption, designers mix low-leakage, low performance transistors with high performance, high-leakage transistors (hereinafter referred to as “standard transistors”) by using the low-leakage transistors for circuit elements that do not require high performance. This may be done by, for instance, initially designing the circuit using logic cells comprised entirely of standard transistors. The circuit can then be analyzed to identify those logic cells in which there is a “delay margin”, i.e., those logic cells whose time to change state is not critical to the performance of the overall circuit. The logic cells with a delay margin can then be replaced with equivalent logic cells that use low-leakage, low performance transistors. Alternately, the initial circuit may be designed using only low-leakage, low performance logic cells. The design may then be analyzed to identify the logic cells that fail timing requirements, and those logic cells replaced with equivalent logic cells that use standard transistors.
The major problem with both of these approaches is that they have unpredictable results. In particular, it is not possible to know if the final design's performance and/or leakage requirements will be achieved until the end of the integrated circuit design process, meaning that multiple design iterations are usually necessary to achieve a required result. Moreover, any changes in the logic design late in the development cycle can have unpredictable affects on the final performance.
What is needed is a method of combining logic cells made from low leakage, low performance transistors with standard, high performance, high leakage transistors into a circuit that can be designed to have predictable, high performance and low overall leakage, and whose design can be modified at any stage in the development cycle without introducing unpredictable results.